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FreeRTOS Support ArchiveThe FreeRTOS support forum is used to obtain active support directly from Real Time Engineers Ltd. In return for using our top quality software and services for free, we request you play fair and do your bit to help others too! Sign up to receive notifications of new support topics then help where you can.
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IRQ interrupt handlingPosted by Cyber Knight on April 2, 2006 The vector table in the boot.s of ARM7LPC2016, specifies a vector table, and for the IRQ interrupt its loading PC with ldr pc, [pc,#-0xFF0] What this actually does? I have found the VIC memory mapping in the file lpc210x.h. What will happen if there are multiple IRQ interrupts? RE: IRQ interrupt handlingPosted by Nobody/Anonymous on April 2, 2006 This allows auto vectoring to the ISR by reading the address directly from the VIC. Please read the manual for the LPC2106 where this is explained. RE: IRQ interrupt handlingPosted by Cyber Knight on April 2, 2006 Where can I get the manual? RE: IRQ interrupt handlingPosted by Nobody/Anonymous on April 2, 2006 The philips WEB site. RE: IRQ interrupt handlingPosted by Cyber Knight on April 2, 2006 Sir, I didn't find any reference to VECTDATA_IRQ defined in lpc210x.h in the manual. Can u please tell for what this is used for? Let me guess, when an IRQ occurs ,this line in boot.s ldr pc, [pc,#-0xFF0] executes. After that what happens? What is placed in the address [pc,#-0xFF0] ? The starting addresses of ISRs are placed in VectAdddrX ,right? RE: IRQ interrupt handlingPosted by Nobody/Anonymous on April 2, 2006 Take a look at: http://www.semiconductors.philips.com/acrobat/usermanuals/UM_LPC2106_2105_2104_1.pdf Pages 70 and 218. This is where the code comes from.
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