|
|||||||||||||||
FreeRTOS Support ArchiveThe FreeRTOS support forum is used to obtain active support directly from Real Time Engineers Ltd. In return for using our top quality software and services for free, we request you play fair and do your bit to help others too! Sign up to receive notifications of new support topics then help where you can.
Loading
Task Block On Event (e.g. bit value)?Posted by Nobody/Anonymous on April 18, 2006 Hello Richard, Is there a way to write a task that will wait for an event to occur and unblock - that is - something like a bit twiddle? Is there a way to do this? This will be helpful in developing a task that waits - for instance - for a UART RCV char flag that has set - then DMA the RCV char(s) into memory someplace. TIA, John W. RE: Task Block On Event (e.g. bit value)?Posted by Nobody/Anonymous on April 18, 2006 The kernel cannot know a bit has changed unless the bit change causes an interrupt. If an interrupt is generated then a semaphore could be used. If an interrupt was not generated then you would have to check the bit from the tick. RE: Task Block On Event (e.g. bit value)?Posted by Nobody/Anonymous on April 18, 2006 The idea here is to minimize interrupts - hence handing stuff off to the DMA controller. So, a tickHook would have to be used to do this I suppose? Thanks, John W. RE: Task Block On Event (e.g. bit value)?Posted by Jeff Smith on April 18, 2006 DMA uses interrupts too... It doesn't stand for "Digital Magic Aware", you know ;-) RE: Task Block On Event (e.g. bit value)?Posted by Nobody/Anonymous on April 18, 2006 LOL RE: Task Block On Event (e.g. bit value)?Posted by Nobody/Anonymous on April 18, 2006 Some architectures allow you to use DMA with or without interrupts - take a look at the MSP430 - it's up to you if you want to use interrupts or not with the DMA channel controller. Using this method vs. UART RCV IRQ's may help to reduce interrupt latency in an embedded system. Regards, John W.
Copyright (C) Amazon Web Services, Inc. or its affiliates. All rights reserved.
|
|||||||||||||||
NXP tweet showing LPC5500 (ARMv8-M Cortex-M33) running FreeRTOS.
Meet Richard Barry and learn about running FreeRTOS on RISC-V at FOSDEM 2019
Version 10.1.1 of the FreeRTOS kernel is available for immediate download. MIT licensed.
View a recording of the "OTA Update Security and Reliability" webinar, presented by TI and AWS.
FreeRTOS and other embedded software careers at AWS.
