I modeled an ISR handler on the serial.c example (for the dual UARTs on
the Atmel AT91SAM7X256).

I have 2 tasks in my system - one which talks on the Ethernet (lwIP), the
other for an RS-232 console user. This, and the several ISRs (timer,
uarts, etc.) The Ethernet task is essentially idle as the cable is
unplugged.

When I write a long message to the console, I need to have a queue at
least as large as the largest screen paint I do (> 2K) in order for it to
work. If I don't, the task waits forever for the queue to clear, but the
queue doesn't clear even though the interrupt is enabled if I use a
non-zero timeout in the xQueueSend call. The application was ported from
a PIC18 (no OS) and I had no trouble putting out messages larger than the
buffer size.

I found the same problem early on with serial.c, not realizing it was
something inherent rather than a mistake in my code.

I'm wondering - is there something I'm missing here? It seems that it
would be a most basic function to allow other tasks (especially
interrupts) to run while another is blocked for a resource. We're not
talking about priority inversion, just having interrupts operate while a
task is blocked.

Some points:

1) The UART examples are not necessarily designed to be efficient - but rather to test the kernel. Testing the kernel implies generating lots of interrupts and context switches which is probably not what you want in your real application if sending 2K or data. You might be better or using a simple circular buffer, then a semaphore to handle the blocking and waking of the task. Also the demos don't make use (normally) of FIFO's or DMA's so you may want to look at the setup of the UART.

2) Can you confirm that you are not blocking from within the IAR, or making any blocking calls from within the ISR - this would definitely stuff you up if you were.

3) You can certainly run other tasks and interrupts while one task is blocked on a queue or semaphore. Is it possible that there is a rout out of your ISR (for example a switch to another task) that is performed leaving the UART interrupt disabled/not cleared? A context switch must not be performed until both the UART and the interrupt controllers are cleared.

Regards.